1. Field of the Invention
This invention relates generally to patterning thin metal films onto a substrate. More particularly, this invention relates to the use of reflow techniques to redistribute thin films deposited over entire substrates.
2. Discussion
Thin metal films often must be patterned photolithographically using traditional etching or lift-off methods. Such is particularly the case in the fabrication of microelectronics. In the photolithographic patterning process, the film adheres to the substrate in selected areas, leaving other areas blank. A bonding/removal process enables the fabrication of connections where desired and also enables isolating conducting strips or traces where appropriate. Traditional approaches to thin film patterning often prove unsuitable because some metal layers are too thick for lift-off (or removal), while other metal layers are particularly susceptible to contamination from chemicals used during the photolithography process.
For example, when laser diode die bonding or wafer level packaging, indium films have many desirable characteristics, but are often several micrometers thick. These indium films typically oxidize fairly easily, which diminishes the bonding capability of the indium. Further, when indium films are used in wafer level packaging, photolithographic processes increase the likelihood that the indium will oxidize and/or become contaminated. These potentially contaminating processes include baking, rinsing, etching, and the like.
In another type of fabrication process, indium films are patterned by evaporation onto a substrate through shadow masks. The shadow masks have holes in selected areas of the mask in order to cast a shadow onto the substrate where the indium is desirably deposited. While the use of shadow masks significantly decreases the likelihood of contaminating the indium, the shadow mask process introduces several difficulties. First, shadow masks are often difficult to align with the substrate. Second, shadow masks cannot be used with closed curves, such as a circular trace, because the area outlining the closed trace must be attached to the remaining portion of the mask. For example, traditional fabrication techniques of integrated circuits often requires fabricating the electronic devices by fabricating multiples of the device on a silicon wafer, subdividing the electronic wafer into the individual devices, then packaging the electronic device.
In addition, the packaging portion of the integrated circuit process may optionally include hermetically sealing the device to further protect it within its packaging. Newer fabrication techniques desirably fabricate and package (or seal) the integrated circuit devices formed on the wafer before subdividing the wafer. This fabrication process is referred to as wafer level packaging. One method of wafer level packaging is described in U.S. patent application Ser. No. 08/009,530, entitled Mass Simultaneous Sealing and Electrical Connection of Electronic Devices, assigned to the assignee of the present invention and herein incorporated by reference. The above-referenced patent, however, does not exhaustively address the above-described issues of depositing the bonding material (the indium) while minimizing contamination in order to improve the quality of the hermetic sealing.
Therefore, it is desirable to provide a method and apparatus for patterning thin films while minimizing contamination and facilitating placement of the thin films on the substrate to effect suitable alignment of the thin film patterns.